Compute DSP
A Hexagon CDSP is designed as a computation offload device for an SoC. The
V66G_1024 machine contains:
L2VIC interrupt controller
QTimer timer device
This machine will support any Hexagon CPU, but will default to v66.
A Hexagon CDSP is designed as a computation offload device for an SoC. The
V66G_1024 machine contains:
L2VIC interrupt controller
QTimer timer device
This machine will support any Hexagon CPU, but will default to v66.